1. Field of the Invention
The present invention relates to a solid-state imaging apparatus to be used for an image reading apparatus, such as a copier and a scanner, a driving method of the solid-state imaging apparatus, and a camera and copier, both using the solid-state imaging apparatus.
2. Description of the Related Art
For example, Japanese Patent Application Laid-Open No. 2006-211363 (first Patent Document) discloses a solid-state imaging apparatus to be used for an image reading apparatus, such as a copier and a scanner, especially for reading a color image. As illustrated in FIG. 1 of the first Patent Document, the solid-state imaging apparatus is equipped with photodiodes to read a plurality of different color components and has accumulation capacities corresponding to the respective photodiodes.
Japanese Patent Application Laid-Open No. H06-204445 (second Patent Document) illustrates a solid-state imaging apparatus including one common output line. But, if signals are output from respective color components, for example, FIG. 12 of the second Patent Document illustrates another configuration of the solid-state imaging apparatus.
FIG. 4 of Japanese Patent Application Laid-Open No. 2003-087503 (third Patent Document) especially illustrates a color copier of connecting amplifier circuits having amplifying gains peculiar to respective colors to the subsequent stage of a solid-state imaging apparatus.
Accordingly, in order to deal with such a configuration, a configuration of outputting signals through a plurality of common output lines, and of outputting only one color component from each of the common output lines is required. Because the configurations of the second and third Patent Documents perform parallel signal outputting from the plurality of common output lines, the configurations enable their reading time to be faster than that of the first Patent Document by the number of the parallel output lines.
When signals are read from the accumulation capacities of these solid-state imaging apparatus, the signals are read through signal transfer switches in accordance with the gains according to the capacity dividing ratios of the whole capacity of the common output lines and the accumulation capacities. If the capacity value of a common output line is denoted by CH, and the accumulation capacity value thereof is denoted by CT, then the reading gain Gc thereof is expressed by a formula Gc=CT/(CT+CH). Because the reading gain Gc always takes a value less than one, it is also performed to output a signal by multiplying the signal by a gain of one or more in the output circuit at the subsequent state in order to compensate the lost gain.
In addition to the above-mentioned configurations, the configuration disclosed in Japanese Patent Application Laid-Open No. 2003-051989 (fourth Patent Document) is sometimes adopted when the improvement of the performance of S/N ratio is required. The configuration illustrated in FIG. 8 of the fourth Patent Document enables the removal of the noise components that are generated in photodiodes and charge-voltage converting units by providing two accumulation capacity systems for each pixel. Alternatively, the configuration illustrated in FIG. 4 of the fourth Patent Document is equipped with an amplifier circuit in the vertical transfer unit of each pixel. By adopting this configuration, the amplification is performed in the vertical transfer unit, which performs a low speed operation, and consequently noise reduction can be realized in comparison with the case where the amplification is performed in an output circuit, which performs a high speed operation. Furthermore, by adopting the configuration illustrated in FIG. 1 of the fourth Patent Document, the amplification is performed in the low speed operation circuit, removing the noise components generated in the photodiodes and the charge-voltage converting units. Consequently, further noise reduction can be realized.
In the cases of these solid-state imaging apparatus mentioned above, capacity dividing reading is performed from the accumulation capacities to the common output lines, and consequently signals are always read by the gain one or less. Furthermore, for example, in the case of a solid-state imaging apparatus reading an A-4 size original in the lateral direction, which is used in a copier and the like, at 600 dots per inch (DPI), a line sensor is led to include about 7500 pixels arranged at 10 μm pitches. In this case, the common output line has a length of about 7.5 cm, and signal transfer switches of about 7500 pixels at a maximum are connected to the common output line. Consequently, the capacity value CH of the common output line becomes a large value. Accordingly, it is necessary to set the accumulation capacity value CT to a large value or to set the output circuit at the subsequent stage to have a high gain in order to obtain the sufficient reading gain Gc. However, if the latter method is chiefly adopted, the high speed operation circuit is designed to have a high gain, which results in the deterioration of the S/N ratio of the circuit. Accordingly, the accumulation capacity value CT is frequently set to a large value generally.
Although the necessary accumulation capacity value CT depends on a semiconductor process and a circuit size, for example, if it is supposed that a capacity of 15 pF is attached to the capacity value CH of the common output line, then the accumulation capacity value CT is needed to be 0.3 pF when the reading gain Gc is ⅕, and the accumulation capacity value CT is needed to be 0.5 pF when the reading gain Gc is ⅓. For example, if the capacities are formed of metal-oxide-semiconductor (MOS) capacities, then the lengths of the accumulation capacities arranged at 10 μm pitches become 241.3 μm and 144.8 μm in the cases of the reading gains Gc of ⅕ and ⅓, respectively, when the thicknesses of oxide films are 1500 nm. Incidentally, separation spaces between capacitative elements are supposed to be 1 μm.
Attempts of reducing a chip size have been performed in the past in order to reduce manufacturing costs by increasing the number of chips capable of being taken out from a silicon wafer. As the technique of reducing a chip size, the method of realizing the reduction by means of a device of circuits of sharing the circuit elements having larger occupation areas with a plurality of constituent elements exists besides the method of realizing the reduction by the miniaturization of the semiconductor process. In particular, in the above-mentioned solid-state imaging apparatus, the sizes of the accumulation capacities are generally larger among that of each of the constituent elements, it is effective, for example, to reduce the total number of the accumulation capacities by sharing the accumulation capacities with a plurality of pixels, and to reduce the occupation areas of the accumulation capacities for reducing the chip size.
For example, if the accumulation capacities of the configuration of the second Patent Document are shared by the method mentioned above, for example, it is conceivable that the pixels of different color components in a same column share an accumulation capacity. However, in this case, the number of pixels that can read by one time of scanning is: (total number of pixels)/(number of pixels sharing one accumulation capacity). Consequently, the method mentioned above has a problem that a plurality of times of scanning is needed for reading the signals of the total pixels, and that the total reading time of the total pixels becomes longer than that of the conventional configuration by about (number of pixels sharing one accumulation capacity) times.